Thursday, 14 September 2017

Adding L3 Cache in gem5

Its very easy and straightforward approach to add more level of caches hierarchy in gem5 system simulator.

1. Add l3 cache option in Options.py
parser.add_option("--l3cache", action="store_true")

2. Add l3 cache class in Caches.py
class L3Cache(Cache):
assoc = 64
tag_latency = 32
data_latency = 32
response_latency = 32
mshrs = 32
tgts_per_mshr = 24
write_buffers = 16

3. Define a L3XBar class in Xbar.py
class L3XBar(CoherentXBar):
# 256-bit crossbar by default
width = 32
frontend_latency = 1
forward_latency = 0
response_latency = 1
snoop_response_latency = 1
snoop_filter = SnoopFilter(lookup_latency = 0)

4. Import L3XBar from XBar in BaseCPU.py
from XBar import L3XBar

5. Define addThreeLevelCacheHierarchy function in BaseCPU.py
def addThreeLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL2Caches(ic, dc, iwc, dwc)
self.toL3Bus = L3XBar()
self.connectCachedPorts(self.toL3Bus)
self.l3cache = l3c
self.toL3Bus.master = self.l3cache.cpu_side
self._cached_ports = ['l3cache.mem_side']

6. Assign L3Cache to l3_cache_class in CacheConfig.py

7. Finally connect l2, l3 and mem buses in CacheConfig.py
if options.l2cache and options.l3cache:
system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
assoc=options.l2_assoc)

system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l3_size,
assoc=options.l3_assoc)

system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.tol3bus = L3XBar(clk_domain = system.cpu_clk_domain)

system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.tol3bus.slave

system.l3.cpu_side = system.tol3bus.master
system.l3.mem_side = system.membus.slave
at

14 comments:

  1. mmichel9220 December 2017 at 10:33

    Thank you for your tutorial.

    There are two things not clear to me:
    4. Import L3XBar from XBar
    from XBar import L3XBar

    Where should i do that? I have added that to BaseCPU.py

    It is not clear what u mean with:

    6. Assign L3Cache to l3_cache_class in CacheConfig.py


    When I applied everything, I got the following error:
    File "/home/eca/gem5/configs/common/CacheConfig.py", line 106, in config_cache
    system.tol3bus = L3XBar(clk_domain = system.cpu_clk_domain)
    NameError: name 'L3XBar' is not defined

    But if you see its imported.

    ReplyDelete
    Replies
    1. Tanveer Ahmad21 December 2017 at 03:01

      Hi,
      1. Yes, in BaseCPU.py
      2. Just assign/add l3_cache_class next to l2_cache_class and L3Cache next to L2Cache in the following code snippet in CacheConfig.py

      if options.cpu_type == "O3_ARM_v7a_3":
      try:
      from cores.arm.O3_ARM_v7a import *
      except:
      print "O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?"
      sys.exit(1)

      dcache_class, icache_class, l2_cache_class, walk_cache_class = \
      O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \
      O3_ARM_v7aWalkCache
      else:
      dcache_class, icache_class, l2_cache_class, walk_cache_class = \
      L1_DCache, L1_ICache, L2Cache, None

      if buildEnv['TARGET_ISA'] == 'x86':
      walk_cache_class = PageTableWalkerCache


      Hope this will resolve your issue.

      Delete
    2. mmichel9210 January 2018 at 13:42

      Hi,
      Thankyou for you response. I have done all you tips, but still getting the same error as above: name 'L3XBar' is not defined

      Do you have some other tips?

      Best regards

      Delete
    3. Unknown13 January 2018 at 07:34

      Hi mmichel92,
      You need to rebuild gem5 executing 'scons build//gem5.opt' in the gem5 directory.
      Replace with your architecture, I guess ARM since you're following ECA ;)

      Kind regards.

      Delete
  2. Unknown13 January 2018 at 07:33

    This comment has been removed by the author.

    ReplyDelete
  3. tristan7 April 2018 at 19:16

    Thank you for your tutorial.
    But there is an error after I have done all your tips.
    fatal: system.tol3bus.slave[0] cannot sendRangeChange() without master port
    How should I do for this?
    And I don't understand this place.
    def addThreeLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
    Why is l2c not l3c?
    Hope you can help me.

    ReplyDelete
    Replies
    1. Newton3 October 2018 at 22:43

      I am also facing same issue after adding L3 cache

      Delete
    2. Newton3 October 2018 at 23:50

      In CacheConfig.py

      I was able to fix this issue by commenting the line
      system.l2.mem_side = system.membus.slave
      i.e.
      #system.l2.mem_side = system.membus.slave

      in
      if options.l2cache:

      Delete
  4. Unknown31 May 2020 at 21:01

    Hai sir
    I edit all the file, there is no error in my execution, but i cant get the status of L3

    ReplyDelete
  5. Anonymous5 May 2021 at 07:53

    This blog is not fully correct and it is not complete too. However, I have the complete and correct solution for adding L3 cache in the Classical memory model in GEM5. Pl ping me, if you want the solution.

    ReplyDelete
    Replies
    1. Trafalgar6 May 2021 at 23:50

      Hi, how do I get the right answer?

      Delete
    2. Anonymous21 May 2021 at 23:50

      You may contact me on my email : avinashk.iitbombay@gmail.com

      Delete
  6. Avinash10 September 2021 at 09:07

    This comment has been removed by the author.

    ReplyDelete
  7. Avinash13 September 2021 at 15:01

    Detailed solution is available on my account. Just click on my name, and on the new page you will see the solution in my blogs.

    ReplyDelete

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Adding L3 Cache in gem5

Its very easy and straightforward approach to add more level of caches hierarchy in gem5 system simulator. 1. Add l3 cache option in...

  • Adding L3 Cache in gem5
    Its very easy and straightforward approach to add more level of caches hierarchy in gem5 system simulator. 1. Add l3 cache option in...