Its very easy and
straightforward approach to add more level of caches hierarchy in
gem5 system simulator.
1. Add l3 cache
option in Options.py
parser.add_option("--l3cache",
action="store_true")
2. Add l3 cache
class in Caches.py
class
L3Cache(Cache):
assoc = 64
tag_latency = 32
data_latency =
32
response_latency
= 32
mshrs = 32
tgts_per_mshr =
24
write_buffers =
16
3. Define a L3XBar
class in Xbar.py
class
L3XBar(CoherentXBar):
# 256-bit
crossbar by default
width = 32
frontend_latency
= 1
forward_latency
= 0
response_latency
= 1
snoop_response_latency = 1
snoop_filter =
SnoopFilter(lookup_latency = 0)
4. Import L3XBar
from XBar in BaseCPU.py
from XBar import
L3XBar
5. Define
addThreeLevelCacheHierarchy function in BaseCPU.py
def
addThreeLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc =
None):
self.addPrivateSplitL2Caches(ic, dc, iwc, dwc)
self.toL3Bus
= L3XBar()
self.connectCachedPorts(self.toL3Bus)
self.l3cache
= l3c
self.toL3Bus.master = self.l3cache.cpu_side
self._cached_ports = ['l3cache.mem_side']
6. Assign L3Cache to
l3_cache_class in CacheConfig.py
7. Finally connect
l2, l3 and mem buses in CacheConfig.py
if options.l2cache
and options.l3cache:
system.l2 =
l2_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
assoc=options.l2_assoc)
system.l3 =
l3_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l3_size,
assoc=options.l3_assoc)
system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.tol3bus = L3XBar(clk_domain = system.cpu_clk_domain)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.tol3bus.slave
system.l3.cpu_side = system.tol3bus.master
system.l3.mem_side = system.membus.slave
